Derived Logic Gates

#NAND gate
It is the combination of AND and NOT gates which produces low output when all inputs are high, otherwise the output will be high. It is the integration of NOT gate and AND gate that means NOT+ AND = NAND.
     
Graphical Representation of NAND gate
    
       Truth Table of NAND gate

#NOR gate
It is the combination of OR and NOT gates which produces high output when all inputs are low, otherwise the output will be low. It is the integration of NOT gate and OR gate that means NOT+ OR = NOR.
       
Graphical Representation of NOR gate
   
          Truth Table of NOR gate

# Exclusive OR(X-OR) gate
The XNOR gate produces high (1) output when all the inputs are either low (0) or high (1). So, it is an even parity generator. XOR can be written as: F = A’.B + A.B’
               
         Graphical Representation of X-OR gate

                    Truth Table of X-OR gate

# Exclusive NOR(X-NOR) gate
The XNOR gate produces high (1) output when all the inputs are either low (0) or high (1). So, it is a odd parity. XNOR can be written as: F = A.B + A’.B’
        
          Graphical Representation of X-NOR gate

                    Truth Table of X-NOR gate